1. Field of the Invention
The present invention relates to a method of manufacturing a junction in a semiconductor device, and more particularly to a method of manufacturing a junction in a semiconductor device capable of improving a short channel characteristic by suppressing a facet occurred when forming an elevated source/drain junction (ESD) of the buried channel field effect transistors (BC-FETs) using a selective epitaxial growth (SEG) technique as well as capable of increasing the electric current density by lowering the series resistance of source/drain extension.
2. Description of the Prior Arts
Generally, as semiconductor devices become high-integrated, small-sized and high-speed, it is required to improve a short channel characteristic, a junction leakage characteristic and a contact resistance characteristic in the buried channel field effect transistor. The buried channel field effect transistor has been found to show the good improvement in its characteristic when an elevated source/drain junction fabricated by a selective epitaxial growth is applied thereto.
FIGS. 1A to 1C are cross sectional views of the device illustrating a method of manufacturing a conventional semiconductor device.
With reference to FIG. 1A, a device separating film 12 is form on the semiconductor substrate 11 to define an active region, and then a gate oxide film 13, a gate electrode 14 and a mask insulating film 15 are successively formed.
In FIG. 1B, a gate spacer 16 is formed on the side wall of the pattern on which the gate oxide film 13, gate electrode 14 and mask insulating film 15 have successively been deposited, and then a non-doped epi-silicon layer 17 is selectively formed on only an exposed portion of the semiconductor substrate 11 using a chemical vapor deposition (CVD) process. On a portion adjacent the gate side-wall spacer 16 with respect to the epi-silicon layer 17 fabricated by the selective epitaxial growth technique, there occurs a facet 19 having a relatively large angle of 30 to 60.degree.. Herein, prior to growing the epi-silicon layer 17, a native oxide film created on the surface of the semiconductor substrate 11 is removed using a wet cleaning process.
FIG. 1C shows processes for form an elevated source/drain junction. As shown, a source/drain ion implantation process is performed, and then there performed a thermal annealing for activating the ion-implanted dopants. The dopants are diffused into the semiconductor substrate 11 thereby to form a diffusion region 18. As a result, there formed an elevated source/drain junction 178 consisting of the doped epi-silicon layer 17 and the diffusion region 18. In the source/drain ion implantation process, a P-type impurity ion is applied since the buried field effect transistor is P-channel.
In the elevated source/drain junction 178 fabricated by such conventional method, as shown in FIG. 1B, the epi-silicon layer 17 formed using the selective epitaxial growth technique causes a facet 19 to occur on a portion adjacent the gate side-wall spacer 16 with respect to it. Such facet 19 has been disclosed by C. Mazure et al., "IEDM, p853 (1992)". As shown in FIG. 1C, this facet 19 causes a local increase of the depth of the diffusion region 18 formed within the semiconductor substrate 11 beneath the epi-silicon layer 17 upon the source/drain implant. That is, the profile of the diffusion region 18 formed by the source/drain ion implantation process becomes deep in the portion (18A) adjacent the channel, resulting in the increase of the drain induced barrier lowing (DIBL) effect in the elevated source/drain junction 178. As a result, a short channel characteristic becomes worse to the extent that makes an application of the field effect transistor using the buried channel difficult. Such a relationship between the facet 19 and DIBL effect has been discussed by J. J. Sun et al., "IEEE ED-45 [6], p1377 (1998)".
In order to solve the problem due to the facet 19, several improvements have been disclosed by J. J. Sun et al., "IEEE ED-45 [6], p137 (1998)" and C. P. Chao, et at., "IEDM, p103 (1997)". However, these improvements also cause the complexity in other processes. In addition, in order to remove the cause of the local increase of the depth of the diffusion region 18, T. Tanaka et al., "Symp. On VLSI Tech., p88 (1998)" apply a new dopant such as decarborane, B.sub.10 H.sub.14.
In the meantime, K. Miyano et al., "Ext. Abst. Of SSDM, p420 (1998)" disclose that a spacer undercut is induced by a negative slope of the side-wall spacer and thus a silicon is somewhat penetrated into the undercut during the selective epitaxial growth (SPG) process. Also, Jung Ho Lee et al., "J. Kor. Phys. Soc., 33 s302 (1998)" discloses that the facet may be minimized by the aid of the stacking fault (SF).